This invention is applicable to data processing systems with multi-level memory where the second level (L2) memory used for both unified (code and instructions) level two cache and flat (L2 SRAM) memory used to hold critical data and instructions. The second level memory (L2) is used for multiple purposes including unified instruction and data level two cache, directly addressable SRAM memory used to hold critical data and code accessible by both external and internal direct memory access (DMA) units.
When the level one data cache controller is granted access to the level one data cache, this access could force an existing line to be evicted. The CPU can also force the level one data cache to evict lines though the block writeback operation. At the same time, the level two cache could be receiving a DMA access to the same line. This situation could break coherency, if DMA data were committed incorrectly. This could occur by writing to the level two memory then overwriting that data with the level one cache victim. This could also occur by sending the DMA data as a snoop write to the level one data cache. This forces the level one data cache to write the DMA data to its cache after the victim has been evicted. This effectively, drops the DMA write. Thus when a victim is in progress, a DMA write sent as snoop could miss the victim.
Cached coherent memory systems must enforce an in-order pipeline to maintain coherence across all coherent master caches and coherent memory endpoints. A typical non-coherent memory request pipeline includes: Command (Read or Write) Bus; Write Data Bus; Read Data Bus; and Write Status Bus. To maintain coherence the memory controller needs to be able to request the latest data for a memory location from a master cache via either forced eviction or a non-evicting data update. Once this new data gets to the memory controller, it can be committed when any subsequent coherent memory access can commit. If the snoop returns travel along the same busses above they can be blocked by other possibly coherent requests. If the memory controller stalls coherent requests to wait for a snoop return and the snoop return is stuck behind coherent memory requests, the pipeline is deadlocked.
In the most difficult scenario the master cache has begun evicting a cache line and subsequently receives a snoop request to the same line. In this invention the master cache waits for the eviction to complete before responding to the snoop. Under these conditions it is critical that the victim not also be blocked by coherent requests.